1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which has an internal power supply voltage generating circuit for generating a plurality of internal power supply voltages at different voltage levels.
2. Description of the Background Art
FIG. 17 schematically shows a whole structure of a semiconductor memory device in the prior art. In FIG. 17, a semiconductor memory device includes a memory cell array 900 which has a plurality of memory cells MC arranged in a matrix form. In this memory cell array 900, a word line WL is arranged corresponding to each row of memory cells MC, and a bit line pair BLP is arranged corresponding to each column of memory cells MC. Each word line WL is connected to memory cells MC in the corresponding row, and each bit line pair BLP is connected to memory cells MC in the corresponding column. As will be described later further in detail, each bit line pair BLP has bit lines BL and /BL transmitting data signals complementary with each other.
The semiconductor memory device further includes an address buffer 902 which receives an externally supplied address signal and generates an internal address signal, a row select circuit 904 which drives the word line corresponding to an addressed row in memory cell array 900 to the selected state in accordance with an internal row address signal generated from address buffer 902, a column select circuit 906 which generates a column select signal for selecting the addressed column in memory cell array 900 in accordance with an internal column address signal generated from address buffer 902, sense amplifiers which are arranged corresponding to the respective bit line pairs BLP in memory cell array 900 for differentially amplifying potentials on the corresponding bit line pairs when made active, and I/O gates which connect a bit line pair corresponding to an addressed column in memory cell array 900 to an internal I/O bus line 907 in accordance with the column select signal generated from column select circuit 906, respectively. In FIG. 17, the sense amplifiers and the I/O gates are represented by one block 908.
The semiconductor memory device further includes an I/O buffer 910 for performing input/output of data into and from the device, and a read/write circuit 912 for transmitting internal data between I/O buffer 910 and internal I/O line 907. Read/write circuit 912 includes a preamplifier which amplifies memory cell data read from memory cell array 900 for transmission to an output buffer included in I/O buffer 910, and a write driver which produces and transmits write data to internal I/O bus 907 at a predetermined timing in accordance with the internal write data received from an input buffer included in I/O buffer 910.
Further, the semiconductor memory device includes a timing control circuit 914, which receives externally supplied control clock signals, i.e., a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, and generates control signals for controlling operations related to the row selection and input/output of data, and an ATD circuit 916 which operates in accordance with the internal signal from timing control circuit 914, and detects a transition in the internal column address signal from address buffer 902. An address transition detection signal ATD generated from ATD circuit 916 is applied to timing control circuit 914 for determining operation timings of the circuits related to the column selection.
Row address strobe signal /RAS determines a standby cycle and an active cycle of this semiconductor memory device. When row address strobe signal /RAS is activated and attains L-level, the semiconductor memory device enters the active cycle and performs the memory cell selecting operation. Column address strobe signal /CAS determines the timing for latching the column address signal and the timing for input/output of data. Write enable signal /WE designates the mode for writing/reading data. The timing of reading out data is determined by activation of column address strobe signal /CAS. The timing of data input is determined by activation of both column address strobe signal /CAS and write enable signal /WE.
ATD circuit 916 is activated at a predetermined timing after row address strobe signal /RAS is activated, and determines the operation timings of column select circuit 906 and read/write circuit 912 as well as the timing of internally reading out data at I/O buffer 910.
In the following description, the term "row-related operations" represents a series of operations staring from input of a row address to amplification of stored data in the corresponding memory cells by the sense amplifiers. The term "column-related operations" represents operations starting from input of a column address to connection of an addressed bit line pair to the internal I/O line pair and subsequent reading/writing of data from or into the memory cell. The row-related operation is driven by row address strobe signal /RAS. The column-related operation is triggered by address transition detection signal ATD. Usually, column address strobe signal /CAS drives the column-related operation. However, the address access time from application of the address signal to data reading depends on specifications, and the triggering by the address transition detection signal ATD is employed for performing operations accurately based on this access time.
FIG. 18 schematically shows a structure of a portion in memory cell array 900 and block 908 related to one column in the semiconductor memory device shown in FIG. 17. In FIG. 18, bit line pair BLP has bit lines BL and /BL which are complementary with each other. Bit line pair BLP is connected to memory cells MC on one column. FIG. 18 representatively shows a memory cell MC arranged corresponding to a crossing between one word line WL and bit line BL. Memory cell MC includes a memory cell capacitor MQ for storing information, and an access transistor MT formed of an n-channel MOS transistor which is turned on to connect memory cell capacitor MQ to corresponding bit line BL in response to a signal potential on word line WL. Memory cell capacitor MQ is supplied on one electrode node, i.e., cell plate electrode node with a cell plate voltage Vcp of a constant value equal to half the power supply voltage. Based on this cell plate voltage Vcp, positive or negative electric charges are accumulated on the other electrode node, i.e., storage node of the memory cell capacitor MQ.
For bit lines BL and /BL, there is arranged an equalize/precharge circuit 901 for equalizing bit lines BL and /BL to an intermediate voltage Vb1 in response to a bit line equalize instructing signal .phi.BQ. This bit line precharge voltage Vb1 is also at the intermediate voltage level equal to half the power supply voltage Vcc. Bit line equalize instructing signal .phi.BQ is active during the standby cycle, and is inactive during the active cycle.
Block 908 of the sense amplifiers and I/O gates includes a sense amplifier circuit 908a which is provided for each bit line pair BL and /BL, and is activated to amplify differentially potentials on bit lines BL and /BL in response to activation of sense amplifier activating signal .phi.SA, and an I/O gate circuit 908b which is turned on in accordance with column select signal CSL from column select circuit 906 (see FIG. 17), and connects bit lines BL and /BL to an internal data line pair 907a included in internal I/O bus 907. I/O gate circuit 908b includes n-channel MOS transistors provided for bit lines BL and /BL, respectively. An operation of the semiconductor memory device shown in FIGS. 17 and 18 will be described below with reference to a waveform diagram of FIG. 19.
Before time t1, row address strobe signal /RAS is at H-level and inactive, and the semiconductor memory device is in the standby cycle. In this state, bit line equalize instructing signal .phi.BQ is at H-level and inactive, so that equalize/precharge circuit 901 is activated, and bit lines BL and /BL are precharged to the intermediate level of Vb1. Word line WL is in the nonselected state and at L-level, and column select signal CSL is also in the nonselected state of L-level.
At time t1, row address strobe signal /RAS falls to L-level, so that the active cycle starts, and the memory cell select operation starts. In accordance with falling of row address strobe signal /RAS, externally applied address signal AD is taken and applied into row select circuit 904 as a row address signal X. Row select circuit 904 is activated under the control of timing control circuit 914, and drives word line WL provided corresponding to the row X corresponding to row address signal X to the selected state. In response to falling of row address strobe signal /RAS, bit line equalize instructing signal .phi.BQ is set to the inactive state of L-level, so that equalize/precharge circuit 901 is deactivated, and bit lines BL and /BL are electrically floated at precharge voltage Vb1.
When word line WL is selected to have potential raised, access transistor MT shown in FIG. 18 is turned on, and charges accumulated in memory cell capacitor MQ are transmitted onto bit line BL. FIG. 19 shows, as an example, change in potential on bit line BL in the case where memory cell MC has stored data of H-level. When a potential difference between bit lines BL and /BL sufficiently increases, sense amplifier activation signal .phi.SA is activated, and sense amplifier circuit 908a (see FIG. 18) differentially amplifies the potentials on bit lines BL and /BL. Thereby, the potential on bit line BL attains the power supply voltage Vcc level, i.e., H-level, and the potential on bit line /BL attains the ground voltage level, i.e., L-level.
In parallel with this sensing operation of the sense amplifier, the address signal is taken in as a column address signal Y in accordance with column address strobe signal /CAS, and the column select operation starts. This column select operation is actually performed after completion of the sensing operation of the sense amplifier. After the sensing operation is completed at time t2, the column select operation is performed in accordance with column address strobe signal /CAS. At time t3, column select signal CSL attains H-level or the selected state, so that I/O gate circuit 908b is turned on, and bit lines BL and /BL are connected to internal I/O line pair 907a. Internal I/O line pair 907a has been equalized by an equalize circuit (not shown), and the potentials on internal data line pair 907a are driven by sense amplifier circuit 908a to H- and L-levels, respectively. Thereafter, writing/reading of data for the selected column is performed.
Then, row address strobe signal /RAS is deactivated to attain H-level, so that the potential on word line WL lowers to L-level, and sense amplifier activating signal .phi.SA is deactivated. Then, bit line equalize instructing signal .phi.BQ attains the active state of H-level. Thereby, bit lines BL and /BL are precharged and equalized again to the intermediate voltage level, i.e., precharge voltage Vb1 level. When column address strobe signal /CAS is deactivated to attain H-level, column select signal CSL falls to L-level.
FIG. 20 schematically shows a structure including the timing control circuit, row select circuit and column select circuit in the semiconductor memory device shown in FIG. 17. In FIG. 20, word line WL, bit line pair BLP and I/O gate circuit 908b connected to bit line pair BLP are representatively shown as components in memory cell array 900.
Timing control circuit 914 includes an RAS buffer 914a which receives externally applied row address strobe signal /RAS and produces internal row address strobe signal int/RAS, an address control circuit 914b which produces signals RAL, RADE and CAI for controlling the address take-in timing in accordance with internal row address strobe signal int/RAS, a bit line equalize control circuit 914c which generates bit line equalize instructing signal .phi.BQ in accordance with internal row address strobe signal /RAS from RAS buffer 914a, a word line drive control circuit 914d which generate a word line drive signal RX determining a timing of driving of the word line to the selected state in accordance with internal row address strobe signal int/RAS, and a sense amplifier control circuit 914e which generates sense amplifier activating signal .phi.SA in accordance with internal row address strobe signal /RAS and bit line equalize instructing signal .phi.BQ generated from bit line equalize control circuit 914c.
The timing control circuit 914 further includes a column-related interlock control circuit 914f which produces column address enable signal CADE and column enable signal /CE for controlling operations of the column-related circuits. Column-related interlock control circuit 914f drives column enable signal /CE and column address enable signal CADE to the active state when a predetermined time elapses after sense amplifier activating signal .phi.SA is activated. In accordance with activation of column address enable signal /CE, the column-related circuits are enabled. In accordance with activation of column address strobe signal CADE, production of the internal column address is allowed.
Timing control circuit 914 further includes a CAS buffer 914g which receives externally applied column address strobe signal /CAS and produces a column address latch instructing signal CAL, an output control circuit 914i which produces a data transfer instructing signal DT for controlling transmission of data to an output buffer from a read circuit (preamplifier) included in a read/write circuit in accordance with write enable signal /WE and the internal column address strobe signal from CAS buffer 914g, and a column-related control circuit 914h which generates control signals for the column-related circuits in accordance with the address transition detection signal from ATD circuit 916. As the signals generated from column-related control circuit 914h, FIG. 20 shows a column decoder enable signal CDE to column decoder (column select circuit) 906a, and an equalize instructing signal IOEQ to I/O equalize circuit 920 provided to internal data line pair 907a.
Column decoder 906a is included in column select circuit 906 shown in FIG. 17. Column select circuit 906 may include a column predecoder. Column decoder 906a generates column select signal CSL to I/O gate circuit 908b. I/O equalize circuit 920 equalizes potentials on internal data line pair 907a when data line equalize instructing signal IOEQ is active.
Address buffer 902 includes a row address buffer 902r which receives the externally applied address signal and generates the internal row address signal, and a column address buffer 902c which receives the externally applied address signal and generates the internal column address signal.
Row address buffer 902r includes an address latch circuit 902ra which takes in and latches the externally applied address signal in accordance with row address latch instructing signal RAL from address control circuit 914b, and an internal address generating circuit 902rb which generates complementary internal row address signals in accordance with the internal row address signal from row address latch circuit 902ra in response to activation of row address enable signal RADE from address control circuit 914b.
The complementary internal row address signals generated from internal address generating circuit 902rb are applied to a row decoder/driver 904a included in the row select circuit. Row decoder/driver 904a decodes the address signal from internal address generating circuit 902rb, and drives the word line corresponding to the addressed row to the selected state in accordance with word line drive signal RX from word line drive control circuit 902d. Row select circuit 904 may include a row predecoder in addition to row decoder/driver 904a.
ATD circuit 916 is activated in response to activation of column enable signal /CE from column-related interlock control circuit 914f. Now, an operation of the timing control circuit shown in FIG. 20 will be described below with reference to signal waveform diagrams of FIGS. 21 and 22.
Referring to FIG. 21, description will first be given on an operation in the case where column address strobe signal /CAS is activated prior to activation of column enable signal /CE.
Before time t1, row address strobe signal /RAS and column address strobe signal /CAS are at H-level or inactive. The semiconductor memory device is in standby state. Row address latch instructing signal RAL from address control circuit 914b is inactive, and column address inhibiting signal CAI is active. In this state, row address latch circuit 902ra generates the internal address signal in accordance with the externally applied address signal. Column address buffer 902c is inhibited from taking in the externally applied address signal in accordance with activation of column address inhibiting signal CAI. I/O equalize circuit 920 equalizes internal data line pair 907a to a predetermined voltage level in accordance with activation of data line equalize instructing signal IOEQ.
When row address strobe signal /RAS falls to L-level and is activated at time t1, the active cycle starts. In response to falling of row address strobe signal /RAS, bit line equalize instructing signal .phi.BQ generated from bit line equalize control circuit 914c attains L-level, so that equalization of the bit line pair stops. In response to falling of row address strobe signal /RAS, row address latch instructing signal RAL rises to H-level, and the address latch circuit 902ra attains the latching state. Then, row address enable signal RADE is activated, and the complementary internal row address signals from internal address generating circuit 902rb attain states according to the address signal latched by address latch circuit 902ra.
When address latch circuit 902ra completes latching of the row address, column address inhibiting signal CAI is deactivated, and column address buffer 902c is enabled to take in the externally supplied address signal.
The row select operation is performed in accordance with address signal X which is taken in and latched in accordance with falling of row address strobe signal /RAS. More specifically, word line drive control circuit 914d generates word line drive signal RX at a predetermined timing, and row decoder/driver 904a drives the addressed word line to the selected state in accordance with word line drive signal RX. Then, sense amplifier activating signal .phi.SA generated from sense amplifier control circuit 914e is activated at time t2, so that sensing and amplification of data of the memory cells connected to the selected word line are performed.
At time t2 after a delay from activation of sense amplifier activating signal .phi.SA, column address strobe signal /CAS attains the active state of L-level, and correspondingly column address latch instructing signal CAL attains the active state of H-level. Thereby, column address buffer 902c latches the externally applied address signal. In this state, column enable signal /CE is still inactive, and ATD circuit 916 is also inactive. Further, column address enable signal CADE is inactive. All the internal column address signals from column address buffer 902c are inactive, so that the column select operation is not performed.
At time t3 after elapse of a predetermined time from activation of sense amplifier activating signal .phi.SA, column enable signal /CE from column-related interlock control circuit 914f attains the active state of L-level, and column address enable signal CADE also attains the active state of H-level. Although the address signal changes its level before time t2, the column enable signal /CE is kept at the inactive state of H-level, and the address transition detection signal ATD holds H-level. In accordance with activation of this column address enable signal CADE, the internal address signal from column address buffer 902c attains the state corresponding to the address signal which has already been latched. ATD circuit 916 is activated to lower the address transition detection signal ATD to L-level for application to column-related control circuit 914h in response to activation of column enable signal /CE. Column related control circuit 914h drives column decoder enable signal CDE to the active state in response to falling of address transition detection signal ATD. Responsively, column decoder 906a decodes the complementary internal column address signals from column address buffer 902c, and drives column select signal CSL to the selected state for driving the addressed column to the selected state.
At the same time, column related control circuit 914h drives internal data line equalize instructing signal IOEQ to the inactive state, so that I/O equalize circuit 920 is deactivated and stops equalizing of the internal data line. Thereby, data on bit line pair BLP is transmitted through I/O gate circuit 908b onto internal data line pair 907a, and is further transmitted to the read/write circuit, whereby data is written into or read from the selected memory cell.
At time t4, row address strobe signal /RAS rises to H-level, so that the semiconductor memory device returns to the standby state. In response to rising of row address strobe signal /RAS, row address enable signal RADE attains the inactive state of L-level, and subsequently the row address latch instructing signal RAL attains the inactive state of L-level. Thereby, the address latch circuit 902ra is set to the state for incorporating the externally applied address signal. Also, internal address generating circuit 902rb drives the internal address signal together with its complementary internal address signal to the nonselected state.
In response to rising of row address strobe signal /RAS, word line drive signal RX and sense amplifier activating signal .phi.SA are driven to the inactive state. In response to deactivation of sense amplifier activating signal .phi.SA, column address enable signal CADE and column enable signal /CE are deactivated.
In response to rising of row address strobe signal /RAS, column address inhibiting signal CAI rises to H-level, so that column address buffer 902c is inhibited from taking in the externally applied address signal. Also, column enable signal /CE is set to the inactive state of H-level, and responsively address transition detection signal ATD from ATD circuit 916 rises to H-level. Column decoder enable signal CDE is deactivated, and I/O equalize circuit 920 is activated to equalize internal data line pair 907a to a predetermined voltage level in response to activation of internal data line equalize instructing signal IOEQ.
Then, column address strobe signal /CAS rises to H-level, and column address latch instructing signal CAL attains L-level. Further, bit line equalize instructing signal .phi.BQ is set to the active state of H-level, and potentials on bit line pair BLP is precharged and equalized.
In the operation shown in FIG. 21, if column address strobe signal /CAS is activated prior to activation of column enable signal /CE, the column select operation starts in accordance with the activation of column enable signal /CE, so that the selected memory cell is accessed.
Referring to FIG. 22, description will be given on an operation in the case where column address strobe signal /CAS is set to the active state of L-level after activation of column enable signal /CE.
At time t0, row address strobe signal /RAS is set to the active state of L-level. In accordance with activation of row address strobe signal /RAS, currently applied address signal AD is taken in as row address signal (X) for performing the row select operation. In accordance with this select operation, data of the memory cells connected to the selected word line are read onto the corresponding bit lines, respectively. FIG. 22 representatively shows two bit line pairs BLP0 and BLP1. FIG. 22 specifically shows, by way of example, waveforms in such a case that data of H-level is read onto bit line pair BLP0, and data of L-level is read onto bit line pair BLP1.
In this state, column enable signal /CE and column address enable signal CADE are both inactive, and generation of the internal column address signal and column select operation are inhibited.
When the sense amplifier is activated and data signals on each bit line pair are fixed at H- and L-levels in accordance with the selected memory cell data, respectively, column address enable signal CADE and column enable signal /CE from the column related interlock control circuit shown in FIG. 20 are activated at time t1. Since row address strobe signal /RAS is in the active state of L-level and column address strobe signal /CAS is at H-level, column address buffer 902c takes in the applied address signal, and generates the complementary column address signals in accordance with column address enable signal CADE. The internal column address signal from column address buffer 902c has already changed its state, and ATD circuit 916 lowers address transition detection signal ATD to L-level in response to falling of column enable signal /CE.
In response to falling of address transition detection signal ATD, column decoder enable signal CDE is activated, and internal data line equalize instructing signal IOEQ is deactivated. Then, column decoder 906a performs the column select operation in accordance with currently applied address signal Y0. FIG. 22 shows a waveform in such a case that bit line pair BLP0 is selected in accordance with column address signal Y0, and data of H-level on bit line pair BLP0 is read.
At time t2, the address signal changes its state. Even in this state, column address strobe signal /CAS is still at H-level, and ATD circuit 916 generates address transition detection signal ATD of one shot. In response to activation (rising) of address transition detection signal ATD, column decoder enable signal CDE is set to the inactive state of L-level, and internal data line equalize instructing signal IOEQ is set to the active state at H-level. Thereby, the column select operation according to internal column address signal Y0 stops. Bit line pair BLP0 is isolated from internal data line pair 907a, and I/O equalize circuit 920 equalizes internal data line pair 907a to a predetermined voltage level.
This address transition detection signal ATD is a pulse signal of one shot having a predetermined time width. When address transition detection signal ATD falls to L-level again, column decoder enable signal CDE is activated, and internal data line equalize instructing signal IOEQ is set to the inactive state of L-level. Thereby, the operation of equalizing internal data line pair 907a is completed, and the column select operation is performed in accordance with address signal Y1. Also, bit line pair BLP1 is connected to internal data line pair 907a.
At time t3, equalizing of internal data line pair 907a is to be completed. Even if equalizing of internal data line pair 907a is not yet completed at this time t3, the sense amplifier circuit provided at bit line pair BLP1 functions to change the data on internal data line pair 907a in accordance with data of L level on bit line pair BLP1.
At time t4, column address strobe signal /CAS falls to L-level. Thereby, column address latch instructing signal CAL shown in FIG. 19 is activated, and column address buffer 902c attains the address latching state. While this state is kept, the internal column address signal does not change.
As shown in FIG. 22, column address strobe signal /CAS may be activated after activation of column enable signal /CE. In this case, column address buffer 902c is activated even if internal row address signal X of address signal AD does not change. Column address buffer 902c thus activated produces the complementary internal column address signals in accordance with the currently applied address signal, and lowers address transition detection signal ATD to L-level for column selection in accordance with activation of column enable signal /CE. When the address signal changes thereafter, address transition detection signal ATD from ATD circuit 916 is activated, so that the column select operation is performed. This operation is repeated in accordance with transition in the address signal and the column-related circuits operate until column address strobe signal /CAS is activated. Column address strobe signal /CAS functions only to provide timings for externally inputting and outputting data and a timing for latching the column address signal.
In this case, a period for equalizing internal data line pair 907a depends on a pulse width of address transition detection signal ATD. If address transition detection signal ATD has a sufficiently large pulse width, i.e., if internal data line equalize instructing signal IOEQ has a sufficiently large pulse width, the internal data line pair is reliably equalized to a predetermined voltage level. In this case, however, the column select operation starts with a delay, so that fast access cannot be achieved. Therefore, it is impossible to increase the period for equalizing the internal data line pair (the column decoder is activated after deactivation of the internal data line pair equalize signal). The column select operation described above usually occurs in the fast serial access mode such as a page mode, and it is necessary to provide a countermeasure for reliably reading memory cell data even in the case of insufficient equalizing of the internal data line pair.
FIG. 23 shows a structure of a portion including the sense amplifier circuit and I/O gate circuit. In FIG. 23, sense amplifier circuit SA (908a) includes a p-channel MOS transistor P1 which has a one conduction node connected to a sense node SNDa and a gate connected to a sense node SNDb, a p-channel MOS transistor P2 which has a one conduction node connected to sense node SNDb and a gate connected to sense node SNDa, and a p-channel MOS transistor P3 which is responsive to activation of a sense amplifier activating signal .phi.SP for transmitting power supply voltage Vcc to the other conduction node (source) of each of p-channel MOS transistors P1 and P2. Sense node SNDa is located on bit line BL, and sense node SNDb is located on bit line /BL.
Sense amplifier circuit SA further includes an n-channel MOS transistor N1 which has a one conduction node connected to sense node SNDa and a gate connected to sense node SNDb, an n-channel MOS transistor N2 which has a one conduction node connected to sense node SNDb and a gate connected to sense node SNDa, and an n-channel MOS transistor N3 which is turned on, in response to activation of sense amplifier activating signal .phi.SN, to transmit ground voltage Vss to the other conduction node terminal (source) of each of n-channel MOS transistors N1 and N2.
This sense amplifier circuit SA drives one of sense nodes SNDa and SNDb, which is at a higher potential, to power supply voltage Vcc level, and also drives the other at a lower potential to the ground voltage level.
I/O gate circuit 908b includes transfer gates Ta and Tb each formed of an n-channel MOS transistor and turned on to connect bit lines BL and /BL to internal data bus lines 907aa and 907bb, respectively in response to activation of column select signal CSLa. I/O equalize circuit 920 is provided for internal data bus lines 907aa and 907ab. I/O equalize circuit 920 includes an n-channel MOS transistor, which is turned on to electrically short-circuits internal data lines 907aa and 907ab in response to activation of internal data line equalize instructing signal IOEQ. An operation of the sense amplifier circuit and I/O gate circuit shown in FIG. 23 will be briefly described below.
In the following operation, it is assumed that, as shown in FIG. 23, the potential on bit line BL is at ground voltage Vss level, or at L-level, and bit line /BL is at power supply voltage Vcc level or at H-level. Data of H-level has been read onto internal data lines 907aa and 907ab from unillustrated another bit line pair, so that internal data lines 907aa and 907ab are at H- and L-levels, respectively. Further, a parasitic capacitance Cp is present at each of internal data lines 907aa and 907ab.
As shown in FIG. 24, data is read onto the internal data lines 907aa and 907ab from the unillustrated bit line pair, so that the potentials on internal data lines 907aa and 907ab are at H- and L-levels, respectively. When the address signal changes, internal data line equalize instructing signal IOEQ is activated to attain H-level at time ta, so that internal data lines 907aa and 907ab are electrically short-circuited, and the potentials thereon change toward the intermediate potential level. This change in potential is caused by transfer of electric charges accumulated in parasitic capacitance Cp. When internal data line equalize instructing signal IOEQ is deactivated at time tb, equalizing of internal data lines 907aa and 907ab stops. At time tb, the potentials on internal data lines 907aa and 907ab are not completely equalized, and the potential on internal data line 907aa is at a level slightly higher than that on internal data line 907ab.
In this state, column select signal CSLa is driven to the selected state at time tb, and I/O gate circuit 908b is turned on, so that bit lines BL and /BL are electrically connected to internal data lines 907aa and 907ab. Sense amplifier circuit SA holds the potentials on bit lines BL and /BL at L- and H-levels through sense nodes SNDa and SNDb, respectively. When sense nodes SNDa and SNDb are and electrically connected to internal data lines 907a and 907b rapidly in this state, the potentials on sense nodes SNDa and SNDb change. Sense amplifier circuit SA is required to drive the newly added parasitic capacitance Cp which is charged to the opposite data (data reverse in logic) potential. Therefore, the voltage level of the sense amplifier lowers from power supply voltage Vcc level, and accordingly the drive capability of the sense amplifier lowers. When the potentials on sense nodes SNDa and SNDb rapidly change due to the opposite data, sense amplifier circuit SA cannot hold the original data, and its latch state is inverted, so that the potential levels on bit lines BL and /BL change to H- and L-level, respectively, and the memory cell data is inverted.
In order to prevent inversion of the data which may be caused by this conflict or collision of data, change in potential level on sense nodes SNDa and SNDb of the sense amplifier must be relatively slow, and it is also necessary to keep a balance between the driving capabilities of transfer gates Ta and Tb included in I/O gate circuit 908b and the driving capabilities of MOS transistors P1-P3 and N1-N3 forming the sense amplifier. If the potentials on sense nodes SNDa and SNDb rapidly change as shown in FIG. 25, the latching state of the sense amplifier is inverted in accordance with this rapid potential change. Conversely, if the potentials on the sense nodes change slowly, the original latching state is held.
Therefore, even when the collision of data occurs due to insufficient equalizing of internal data lines 907aa and 907ab, it is necessary to prevent inversion of the latching state of the sense amplifier circuit. If the driving capability powers of transfer gates Ta and Tb are sufficiently reduced for reducing a speed of voltage change at sense nodes SNDa and SNDb, the potentials on sense nodes SNDa and SNDb change slowly in the data write operation, so that fast data writing is impossible. Also, internal data lines 907aa and 907ab cannot be driven fast in accordance with the voltages on sense nodes SNDa and SNDb, and fast data reading is impossible. In order to perform fast and stable writing and reading of data, extremely fine adjustment of sizes is required between MOS transistors P1-P3 and N1-N3 forming the sense amplifier circuit and transfer gates Ta and Tb.
In accordance with increase in storage capacity of the semiconductor memory device, components have been miniaturized, so that the semiconductor memory device must use a low operation power supply voltage for ensuring a reliability of components, reducing a power consumption and achieving a fast operation. This is because the power consumption is proportional to the square of the power supply voltage, and a smaller signal amplitude allows faster charging and discharging of a signal line.
However, MOS transistors which are components of processors in a system have not been miniaturized compared with semiconductor memory devices, and cannot employ the low power supply voltage which is required in the semiconductor memory device. The operation power supply voltage of the semiconductor memory device depends on the system power supply voltage required by the processors and others. Therefore, the semiconductor memory device employs an internal power supply voltage generating circuit, which internally lowers an externally supplied power supply voltage to a desired power supply voltage level for generating an internal power supply voltage. The circuit generating the internal power supply voltage in the above manner is called an internal voltage down converting circuit.
FIG. 26 schematically shows a whole structure of a semiconductor memory device having an internal voltage down converting circuit in the prior art. In FIG. 26, the semiconductor memory device includes an internal voltage down converting circuit 950 which receives an external power supply voltage extVcc and generates an array power supply voltage VccA (i.e., power supply voltage for an array), and an internal voltage down converting circuit 952 which receives external power supply voltage extVcc and generates a peripheral internal power supply voltage VccP (i.e., internal power supply voltage for peripheral circuitry). Internal voltage down converting circuit 950 supplies array internal power supply voltage VccA to an array-related circuit 954. Internal voltage down converting circuit 952 supplies peripheral internal power supply voltage VccP to peripheral circuitry 956. Array-related circuit 954 includes sense amplifiers. Peripheral circuitry 956 includes a read/write circuit, a row select circuit, a column select circuit and a timing control circuit. All the bit line amplitudes in the memory cell array are held at the voltage level of array internal power supply voltage VccA.
Peripheral internal power supply voltage VccP supplied to the peripheral circuit is at a higher level than array internal power supply voltage VccA. By using this relatively high internal power supply voltage VccP, the gate voltage of MOS transistors which are components of the peripheral circuitry is increased, and fast operation of peripheral circuitry 956 is allowed. For array-related circuit 954, the voltage level is kept at a slightly low level in order to ensure a reliability of a dielectric film of a memory cell capacitor, ensure a reliability of a gate insulating film of an access transistor and reducing a current consumption during operation of the sense amplifier.
Particularly in a dynamic semiconductor memory device, a boosted voltage VPP which is higher than array power supply voltage VccA and is nearly equal to 3.multidot.VccA/2 is applied onto the selected word line in order to write data of H-level into a memory cell capacitor without causing a voltage loss by a threshold voltage of an access transistor. For the above reason and for ensuring the reliability of the gate insulating film of the access transistor, the operation power supply voltage of array-related circuit 954 is set to a low value.
FIG. 27 schematically shows voltage levels applied to portions related to one bit line pair. In FIG. 27, memory cell MC is arranged corresponding to a crossing between word line WL and bit line BL. Memory cell MC includes memory cell capacitor MQ storing information, and access transistor MT which connects memory cell capacitor MQ to bit line BL in response to the potential on word line WL. A cell plate electrode node CP of memory cell capacitor MQ is supplied with intermediate voltage Vcp. Cell plate voltage Vcp is at at a level of half the array internal power supply voltage VccA. Although not shown, bit line equalize voltage Vb1 is at a level of half the array internal power supply voltage VccA.
Sense amplifier circuit SA is supplied with array internal power supply voltage VccA and ground voltage Vss as a sense amplifier power supply. Therefore, amplitudes of bit lines BL and /BL are between array internal power supply voltage VccA and ground voltage Vss. The voltage across the storage node SN and cell plate electrode node CP of memory cell capacitor MQ is equal to VccA/2, and therefore the capacitor dielectric film can have a sufficiently high insulation breakdown voltage.
The gate of access transistor MT is supplied with the boosted voltage of 3.multidot.VccA/2. However, array internal power supply voltage VccA is relatively low. Therefore, the gate insulating film of access transistor MT can reliably have desired insulating characteristics.
The column select circuit is supplied with peripheral internal power supply voltage VccP, and the peripheral circuits perform fast operations. In this case, column select signal CSL attains the voltage level equal to peripheral internal power supply voltage VccP when made active, and column select signal CSL at the voltage level of peripheral internal power supply voltage VccP is supplied to gates of transfer gates Ta and Tb included in I/O gate circuit 908b. In this case, the following problem arises.
FIG. 28 shows a relationship between a gate voltage and a drain current of an MOS transistor. The abscissa gives a drain-source voltage Vds, and the ordinate gives a drain current Ids. A curve I represents a relationship between the drain current and drain voltage in the case where the gate-source voltage is equal to a voltage Vgs1, and a curve II represents a relationship between the drain current and drain voltage in the case where the gate-source voltage is equal to a voltage Vgs2. Voltage Vgs1 is higher than voltage Vgs2.
As shown in FIG. 28, a higher gate-source voltage increases a drain current Ids if the drain voltage Vds with reference to the source is constant. More specifically, as the voltage level of column select signal CSL applied to gates of transfer gates Ta and Tb shown in FIG. 27 increases, the current driving capability of transfer gates Ta and Tb increases. Therefore, when column select signal CSL is driven to the selected state in such a state that internal data line pair 907a is equalized insufficiently as already described with reference to FIG. 25, internal data bus line pair 907a is rapidly connected to bit line pair BL and /BL and the potential change occurs due to the opposite data, resulting in a problem that the latched data of sense amplifier circuit SA is inverted.
In order to keep a balance between the sizes of transfer gate transistors Ta and Tb and the sizes of the MOS transistors included in sense amplifier circuit SA in such a case that column select signal CSL is driven to the level of peripheral internal power supply voltage VccP, it is necessary to adjust sizes of transfer gate transistors Ta and Tb and the MOS transistors included in sense amplifier circuit SA in accordance with the voltage level of peripheral internal power supply voltage VccP. Therefore, the relationship in sizes which has already been established cannot be utilized, and redesigning is required. In particular, the voltage levels of internal power supply voltages VccP and VccA have been gradually lowered in accordance with increase in integration density of the semiconductor memory devices, and cannot be set to a fixed value. Therefore, it is necessary to adjust the sizes of MOS transistors included in sense amplifier circuit SA and transfer gate transistors included in I/O gate circuit every time the internal power supply voltage level is changed. This requires a complicated design, and therefore increases a manufacturing cost.